A new logic synthesis and optimization procedure

K. H. Cheng, V. C. Hsieh

Research output: Contribution to journalConference articlepeer-review


The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.

Original languageEnglish
Pages (from-to)IV182-IV185
JournalMaterials Research Society Symposium - Proceedings
StatePublished - 2001
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 24 Apr 200027 Apr 2000


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