A new logic synthesis and optimization procedure

K. H. Cheng; V. C. Hsieh

A new logic synthesis and optimization procedure

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.

Original language	English
Pages (from-to)	IV182-IV185
Journal	Materials Research Society Symposium - Proceedings
Volume	626
State	Published - 2001
Event	Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 24 Apr 2000 → 27 Apr 2000

Cite this

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AB - The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.

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M3 - 會議論文

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SN - 0272-9172

VL - 626

SP - IV182-IV185

JO - Materials Research Society Symposium - Proceedings

JF - Materials Research Society Symposium - Proceedings

T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications

Y2 - 24 April 2000 through 27 April 2000

ER -

A new logic synthesis and optimization procedure

Abstract

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