A new logic synthesis and optimization procedure

Huo Hsing Cheng; Ven Chieh Hsieh

doi:10.1109/ISCAS.2001.922202

A new logic synthesis and optimization procedure

Huo Hsing Cheng, Ven Chieh Hsieh

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	182-185
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922202
State	Published - 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 6 May 2001 → 9 May 2001

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Conference

Conference	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	6/05/01 → 9/05/01

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10.1109/ISCAS.2001.922202

Cite this

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title = "A new logic synthesis and optimization procedure",

abstract = "The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.",

author = "Cheng, {Huo Hsing} and Hsieh, {Ven Chieh}",

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pages = "182--185",

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note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

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Cheng, HH & Hsieh, VC 2001, A new logic synthesis and optimization procedure. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922202, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 182-185, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 6/05/01. https://doi.org/10.1109/ISCAS.2001.922202

A new logic synthesis and optimization procedure. / Cheng, Huo Hsing; Hsieh, Ven Chieh.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 182-185 922202 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The objective of this work is to develop a new logic circuit synthesis and optimization procedure for arbitrary logic function. Following the procedure, we may get a new high performance logic circuit family, which has low power consumption, low power-delay product, area efficiency and suitable for low supply voltage. The new logic family based upon the proposed design procedures has certain advantage over CMOS, DVL and DPL in most cases.

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BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

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Y2 - 6 May 2001 through 9 May 2001

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A new logic synthesis and optimization procedure

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