A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Chih Wen Lu, Chung Len Lee, Jwu E. Chen, Chauchin Su

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this work, a new IDDQ methodology, which is very suitable for testing deep submicron digital ULSI CMOS ICs, is proposed and demonstrated. It incorporates three new BICSs and has advantages of reduction in the circuit partitioning number, low input voltage, high resolution, low power supply voltage, and improved fault detectability and diagnosability.

Original languageEnglish
Title of host publicationProceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998
EditorsSankaran M. Menon, Yashwant K. Malaiya
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)0818691913, 9780818691911
DOIs
StatePublished - 1998
Event1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998 - San Jose, United States
Duration: 12 Nov 199813 Nov 1998

Publication series

NameProceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998
Volume1998-November

Conference

Conference1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998
Country/TerritoryUnited States
CitySan Jose
Period12/11/9813/11/98

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