@inproceedings{80f3ce2a727642f1bcb18ebbf5ff5a68,
title = "A New Design of Ultra-Scaled and High-Density 1-nm Node 6T-SRAM Cell by Lateral-and-Complementary FETs (LC-FETs) with only 21 F2",
abstract = "In this paper, we design and evaluate a new 1-nm-node 6T SRAM cell, the Lateral-and-Complementary FET (LC-FETs) SRAM cell. This SRAM cell can dramatically decrease the layout area to only 23.34\% of that of the N3 FinFET SRAM cell and show comparable performance of the N2 CFET SRAM cell, in terms of the RSNM and WNM values. To further improve the performance of the LC-FET SRAM cell, the pass-gates with more than one (2 or 3) LFETs are then proposed, which shows superior results to those of the N2 or N1 cells.",
keywords = "CFET, LFET, Nanosheet MOSFET, SRAM",
author = "Cheng, \{Kai Wen\} and Liu, \{You Jin\} and \{Ray Hsieh\}, E.",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 ; Conference date: 22-04-2024 Through 25-04-2024",
year = "2024",
doi = "10.1109/VLSITSA60681.2024.10546464",
language = "???core.languages.en\_GB???",
series = "2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings",
}