A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

Guan Xun Chen; Chung Len Lee; Jwu E. Chen

A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

Guan Xun Chen, Chung Len Lee, Jwu E. Chen

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.

Original language	English
Pages (from-to)	58-61
Number of pages	4
Journal	Proceedings of the Asian Test Symposium
State	Published - 2004
Event	Proceedings of the Asian Test Symposium, ATS'04 - Kenting, Taiwan Duration: 15 Nov 2004 → 17 Nov 2004

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AB - In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration.

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M3 - 會議論文

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A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC

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