A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design

Shih Ping Lin, Chung Len Lee, Jwu E. Chen, Ji Jan Chen, Kun Lun Luo, Wen Ching Wu

Research output: Contribution to journalArticlepeer-review

28 Scopus citations

Abstract

The random-like filling strategy pursuing high compression for today's popular test compression schemes introduces large test power. To achieve high compression in conjunction with reducing test power for multiple-scan-chain designs is even harder and very few works were dedicated to solve this problem. This paper proposes and demonstrates a multilayer data copy (MDC) scheme for test compression as well as test power reduction for multiple-scan-chain designs. The scheme utilizes a decoding buffer, which supports fast loading using previous loaded data, to achieve test data compression and test power reduction at the same time. The scheme can be applied automatic test pattern generation (ATPG)-independently or to be incorporated in an ATPG to generate highly compressible and power efficient test sets. Experiment results on benchmarks show that test sets generated by the scheme had large compression and power saving with only a small area design overhead.

Original languageEnglish
Pages (from-to)767-776
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume15
Issue number7
DOIs
StatePublished - Jul 2007

Keywords

  • Circuit testing
  • Low-power testing
  • Test data compression
  • Test pattern generation

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