A multi-code compression technique for reducing system-on-chip test time

Hong Ming Shieh; Chun Shien Wu; Jin Fu Li

doi:10.1109/VDAT.2006.258169

A multi-code compression technique for reducing system-on-chip test time

Hong Ming Shieh, Chun Shien Wu, Jin Fu Li

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

With, the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VISI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than the single-code compression schemes. The area cost of the multi-code decompressor is small - only about 3498μ² based on TSMC 0.18μm standard cell technology.

Original language	English
Title of host publication	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages	239-242
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2006.258169
State	Published - 2007
Event	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan Duration: 26 Apr 2007 → 28 Apr 2007

Publication series

Name	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
Country/Territory	Taiwan
City	Hsinchu
Period	26/04/07 → 28/04/07

Access to Document

10.1109/VDAT.2006.258169

Cite this

Shieh, H. M., Wu, C. S., & Li, J. F. (2007). A multi-code compression technique for reducing system-on-chip test time. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 239-242). Article 4027541 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258169

Shieh, Hong Ming ; Wu, Chun Shien ; Li, Jin Fu. / A multi-code compression technique for reducing system-on-chip test time. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 239-242 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

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abstract = "With, the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes the complexity of SOC testing is much higher than testing conventional VISI chips. One of the test challenges of SOCs is test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than the single-code compression schemes. The area cost of the multi-code decompressor is small - only about 3498μ2 based on TSMC 0.18μm standard cell technology.",

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Shieh, HM, Wu, CS & Li, JF 2007, A multi-code compression technique for reducing system-on-chip test time. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027541, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, pp. 239-242, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, 26/04/07. https://doi.org/10.1109/VDAT.2006.258169

A multi-code compression technique for reducing system-on-chip test time. / Shieh, Hong Ming; Wu, Chun Shien; Li, Jin Fu.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 239-242 4027541 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Shieh HM, Wu CS, Li JF. A multi-code compression technique for reducing system-on-chip test time. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 239-242. 4027541. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2006.258169

A multi-code compression technique for reducing system-on-chip test time

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