A mixed-mode delay-locked loop for widerange operation and multiphase outputs

Keyphrases

• Delay-locked Loop 100%
• Multi-phase Outputs 100%
• Mode Delay 100%
• Mixed Mode 100%
• Time Delay 20%
• Supply Voltage 20%
• Locking Range 20%
• CMOS Process 20%
• SPICE Model 20%
• Jitter Performance 20%
• Delay Cell 20%
• Voltage Controlled Delay Line 20%
• Wide Operation Range 20%
• Lock Time 20%
• Control Delay 20%
• Fast Lock 20%
• Phase Clock 20%
• Low Jitter 20%
• Reference Signal 20%
• Delay Stage 20%
• Phase Range 20%

Engineering

• Locked Loop 100%
• Mixed Mode 100%
• Simulation Result 40%
• Power Supply 20%
• Supply Voltage 20%
• Range Selector 20%
• Range Operation 20%
• Clock Cycle 20%
• Electric Delay Lines 20%
• Delay Time 20%
• Reference Signal 20%