A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

Kuo Hsing Cheng; Yu Lung Lo; Wen Fang Yu; Shu Yin Hung

doi:10.1109/IWSOC.2003.1213012

A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

Kuo Hsing Cheng, Yu Lung Lo, Wen Fang Yu, Shu Yin Hung

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.

Original language	English
Title of host publication	Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
Editors	Yehya Ismail, Wael Badawy
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	90-93
Number of pages	4
ISBN (Electronic)	076951944X, 9780769519449
DOIs	https://doi.org/10.1109/IWSOC.2003.1213012
State	Published - 2003
Event	3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 - Calgary, Canada Duration: 30 Jun 2003 → 2 Jul 2003

Publication series

Name	Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Conference

Conference	3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
Country/Territory	Canada
City	Calgary
Period	30/06/03 → 2/07/03

Keywords

Capacitors
Circuit simulation
Clocks
Delay effects
Delay lines
Filters
Frequency
Phase locked loops
Signal generators
Voltage

Access to Document

10.1109/IWSOC.2003.1213012

Cite this

Cheng, K. H., Lo, Y. L., Yu, W. F., & Hung, S. Y. (2003). A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation. In Y. Ismail, & W. Badawy (Eds.), Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 (pp. 90-93). Article 1213012 (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IWSOC.2003.1213012

Cheng, Kuo Hsing ; Lo, Yu Lung ; Yu, Wen Fang et al. / A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation. Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. editor / Yehya Ismail ; Wael Badawy. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 90-93 (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003).

@inproceedings{0a3c38ed155f4a16be1b9393459d2c4b,

title = "A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation",

abstract = "This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.",

keywords = "Capacitors, Circuit simulation, Clocks, Delay effects, Delay lines, Filters, Frequency, Phase locked loops, Signal generators, Voltage",

author = "Cheng, {Kuo Hsing} and Lo, {Yu Lung} and Yu, {Wen Fang} and Hung, {Shu Yin}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 ; Conference date: 30-06-2003 Through 02-07-2003",

year = "2003",

doi = "10.1109/IWSOC.2003.1213012",

language = "???core.languages.en_GB???",

series = "Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "90--93",

editor = "Yehya Ismail and Wael Badawy",

booktitle = "Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003",

}

Cheng, KH, Lo, YL, Yu, WF & Hung, SY 2003, A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation. in Y Ismail & W Badawy (eds), Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003., 1213012, Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 90-93, 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003, Calgary, Canada, 30/06/03. https://doi.org/10.1109/IWSOC.2003.1213012

A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation. / Cheng, Kuo Hsing; Lo, Yu Lung; Yu, Wen Fang et al.
Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. ed. / Yehya Ismail; Wael Badawy. Institute of Electrical and Electronics Engineers Inc., 2003. p. 90-93 1213012 (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

AU - Cheng, Kuo Hsing

AU - Lo, Yu Lung

AU - Yu, Wen Fang

AU - Hung, Shu Yin

PY - 2003

Y1 - 2003

N2 - This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.

AB - This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.

KW - Capacitors

KW - Circuit simulation

KW - Clocks

KW - Delay effects

KW - Delay lines

KW - Filters

KW - Frequency

KW - Phase locked loops

KW - Signal generators

KW - Voltage

UR - http://www.scopus.com/inward/record.url?scp=43549102367&partnerID=8YFLogxK

U2 - 10.1109/IWSOC.2003.1213012

DO - 10.1109/IWSOC.2003.1213012

M3 - 會議論文篇章

AN - SCOPUS:43549102367

T3 - Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

SP - 90

EP - 93

BT - Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

A2 - Ismail, Yehya

A2 - Badawy, Wael

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Y2 - 30 June 2003 through 2 July 2003

ER -

Cheng KH, Lo YL, Yu WF, Hung SY. A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation. In Ismail Y, Badawy W, editors, Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 90-93. 1213012. (Proceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003). doi: 10.1109/IWSOC.2003.1213012

A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

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