A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation

Kuo Hsing Cheng, Yu Lung Lo, Wen Fang Yu, Shu Yin Hung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.

Original languageEnglish
Title of host publicationProceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
EditorsYehya Ismail, Wael Badawy
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages90-93
Number of pages4
ISBN (Electronic)076951944X, 9780769519449
DOIs
StatePublished - 2003
Event3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003 - Calgary, Canada
Duration: 30 Jun 20032 Jul 2003

Publication series

NameProceedings - 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003

Conference

Conference3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2003
Country/TerritoryCanada
CityCalgary
Period30/06/032/07/03

Keywords

  • Capacitors
  • Circuit simulation
  • Clocks
  • Delay effects
  • Delay lines
  • Filters
  • Frequency
  • Phase locked loops
  • Signal generators
  • Voltage

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