A micro-network on chip with 10-Gb/s transmission link

Wei Chang Liu, Chih Hsien Lin, Shyh Jye Jou, Hung Wen Lu, Chau Chin Su, Kai Wei Hong, Kuo Hsing Cheng, Shyue Wen Yang, Ming Hwa Sheu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm* 1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.

Original languageEnglish
Title of host publicationProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages277-280
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan
Duration: 16 Nov 200918 Nov 2009

Publication series

NameProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Conference

Conference2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Country/TerritoryTaiwan
CityTaipei
Period16/11/0918/11/09

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