Generally, the Log-MAP kernel of the turbo decoding consume large memories in hardware implementtation. In this paper, we propose a new Log-MAP kernel to reduce memory usage. The comparison result shows our proposed architecture can reduce the memory size to 26% of the classical architecture. We also simplify the memory data access in this kernel design without extra address generaters. For 3GPP standard, a prototyping chip of the turbo decoder is implemented to verify the proposed memory-reduced Log- MAP kernel in 3.04×3.04mm2 core area in UMC 0.18um CMOS process.
|Number of pages
|Proceedings - IEEE International Symposium on Circuits and Systems
|Published - 2005
|IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 2005 → 26 May 2005