A low supply voltage synchronous mirror delay with quadrature phase output

Yo Hao Tu, Kuo Hsing Cheng, Chih Hsun Hsu, Hong Yi Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This work proposes a low supply voltage synchronous mirror delay (SMD) circuit with quadrature phase output in intra-chip. In some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, for some specific applications, the circuits need to operate in a low supply voltage environment. In some communication systems, they even need to have I/Q clock signals. Therefore, this is often led to a synchronous circuit with extra functional capabilities. The proposed SMD with the quadrature delay path can operate in the low supply voltage environment by using the low-voltage techniques. The chip is implemented by TSMC CMOS 1P/9M 90 nm technology with a low supply voltage, 0.5 V. The operation range is from 220 MHz to 570 MHz, and the power consumption is 1.95 mW at 570 MHz. The peak-to-peak jitter and RMS jitter of internal clock are 31.78 ps and 3.99 ps at 570 MHz, respectively. The peak-to-peak jitter and RMS jitter of quadrature internal clock are 34.67 ps and 4.48 ps at 570 MHz, respectively. The core area is 188 × 171 um2.

Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
EditorsSerge Bernard, Witold Pleskacz, Dominik Kasprowicz, Lukas Sekanina, Michel Renovell
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages163-166
Number of pages4
ISBN (Electronic)9781479945580
DOIs
StatePublished - 30 Jul 2014
Event17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014 - Warsaw, Poland
Duration: 23 Apr 201425 Apr 2014

Publication series

NameProceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014

Conference

Conference17th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2014
Country/TerritoryPoland
CityWarsaw
Period23/04/1425/04/14

Keywords

  • I/Q clock signals
  • Low supply voltage
  • Quadrature phase output
  • Synchronous mirror delay (SMD)

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