A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

Kuo Hsing Cheng, Wei Bin Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.

Original languageEnglish
Title of host publication2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages263-266
Number of pages4
ISBN (Electronic)0780373634, 9780780373631
DOIs
StatePublished - 2002
Event3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
Duration: 6 Aug 20028 Aug 2002

Publication series

Name2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/TerritoryTaiwan
CityTaipei
Period6/08/028/08/02

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