A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

Kuo Hsing Cheng; Wei Bin Yang

doi:10.1109/APASIC.2002.1031582

A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

Kuo Hsing Cheng, Wei Bin Yang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	263-266
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031582
State	Published - 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan Duration: 6 Aug 2002 → 8 Aug 2002

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan
City	Taipei
Period	6/08/02 → 8/08/02

Access to Document

10.1109/APASIC.2002.1031582

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Cheng, K. H., & Yang, W. B. (2002). A low power, wide operating frequency and high noise immunity half-digital phased-locked loop. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 263-266). Article 1031582 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031582

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title = "A low power, wide operating frequency and high noise immunity half-digital phased-locked loop",

abstract = "In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.",

author = "Cheng, {Kuo Hsing} and Yang, {Wei Bin}",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 ; Conference date: 06-08-2002 Through 08-08-2002",

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series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

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Cheng, KH & Yang, WB 2002, A low power, wide operating frequency and high noise immunity half-digital phased-locked loop. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031582, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 263-266, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, 6/08/02. https://doi.org/10.1109/APASIC.2002.1031582

A low power, wide operating frequency and high noise immunity half-digital phased-locked loop. / Cheng, Kuo Hsing; Yang, Wei Bin.
2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 263-266 1031582 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Cheng, Kuo Hsing

AU - Yang, Wei Bin

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N2 - In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.

AB - In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.

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Cheng KH, Yang WB. A low power, wide operating frequency and high noise immunity half-digital phased-locked loop. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2002. p. 263-266. 1031582. (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). doi: 10.1109/APASIC.2002.1031582

A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

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