A low-power VLSI implementation for variable length decoder in MPEG-1 Layer III

Tsung Han Tsai; Chun Nan Liu; Wen Cheng Chen

doi:10.1117/12.532990

A low-power VLSI implementation for variable length decoder in MPEG-1 Layer III

Tsung Han Tsai, Chun Nan Liu, Wen Cheng Chen

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

MPEG Layer III (MP3) audio coding algorithm is a widely used audio coding standard. It involves several complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length decoding (VLD) e.g. Huffman decoding, is an important part of MP3, which needs great amount of search and memory access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements. The total power saving is about 67%.

Original language	English
Pages (from-to)	30-39
Number of pages	10
Journal	Proceedings of SPIE - The International Society for Optical Engineering
Volume	5309
DOIs	https://doi.org/10.1117/12.532990
State	Published - 2004
Event	Embedded Processors for Multimedia and Communications - San Jose, CA, United States Duration: 19 Jan 2004 → 20 Jan 2004

Keywords

Audio
Low power
MP3
VLSI
Variable length decoder

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10.1117/12.532990

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AB - MPEG Layer III (MP3) audio coding algorithm is a widely used audio coding standard. It involves several complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length decoding (VLD) e.g. Huffman decoding, is an important part of MP3, which needs great amount of search and memory access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements. The total power saving is about 67%.

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T2 - Embedded Processors for Multimedia and Communications

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A low-power VLSI implementation for variable length decoder in MPEG-1 Layer III

Abstract

Keywords

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