Abstract
Modern high-speed CMOS processors using on-chip phase-locked loop (PLL) often require a clock buffer with stringent specifications on the rising time and falling time of the signal rather than on the delay time of the buffer. For these applications, we propose a novel low-power high-driving ability voltage controlled oscillator (LPVCO) used in PLL. The proposed LPVCO is based on the waveform-shaper and split-path CMOS driver techniques to reduce the short-circuit power dissipation and the area requirement than that achievable by the traditional PLL with tapered CMOS buffer. By Hspice simulation results, the power-frequency product of the LPVCO can be reduced by more than 15% in comparison to conventional VCO. Thus, the novel low-power high-driving ability VCO can be used in PLL.
Original language | English |
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Pages (from-to) | 361-375 |
Number of pages | 15 |
Journal | International Journal of Electronics |
Volume | 91 |
Issue number | 6 |
DOIs | |
State | Published - Jun 2004 |