Modern high-speed CMOS processors using on-chip phase-locked loop (PLL) often require a clock buffer with stringent specifications on the rising time and falling time of the signal rather than on the delay time of the buffer. For these applications, we propose a novel low-power high-driving ability voltage controlled oscillator (LPVCO) used in PLL. The proposed LPVCO is based on the waveform-shaper and split-path CMOS driver techniques to reduce the short-circuit power dissipation and the area requirement than that achievable by the traditional PLL with tapered CMOS buffer. By Hspice simulation results, the power-frequency product of the LPVCO can be reduced by more than 15% in comparison to conventional VCO. Thus, the novel low-power high-driving ability VCO can be used in PLL.