A low power all digital IF-discriminator design

Kuo Hsing Cheng; Ta Wei Liu; Yung Hsiang Lin; Jiann Chyi Rau

A low power all digital IF-discriminator design

Kuo Hsing Cheng, Ta Wei Liu, Yung Hsiang Lin, Jiann Chyi Rau

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Chapter › peer-review

Abstract

In this paper, a low power digital intermediate frequency (IF)-discriminator is proposed. A lower frequency reference clock 10kHz is used as the reference frequency in this new IF-discriminator circuit. This new structure utilizes a 4-bit residual-code counter and register to distinguish the difference of input signal frequency. HSPICE simulation result shows that the tolerance margin of the new IF-discriminator for frequency variation is improved effectively.

Original language	English
Title of host publication	Recent Advances in Circuits, Systems and Signal Processing
Publisher	World Scientific and Engineering Academy and Society
Pages	111-113
Number of pages	3
ISBN (Print)	9608052645
State	Published - 2002

Keywords

Frequency-discriminator
Intermediate frequency discriminator
Low power IF-discriminator

Cite this

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AB - In this paper, a low power digital intermediate frequency (IF)-discriminator is proposed. A lower frequency reference clock 10kHz is used as the reference frequency in this new IF-discriminator circuit. This new structure utilizes a 4-bit residual-code counter and register to distinguish the difference of input signal frequency. HSPICE simulation result shows that the tolerance margin of the new IF-discriminator for frequency variation is improved effectively.

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A low power all digital IF-discriminator design

Abstract

Keywords

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