A low jitter self-calibration PLL for 10Gbps SoC transmission links application

Kuo Hsing Cheng; Yu Chang Tsai; Kai Wei Hong; Yen Hsueh Wu

doi:10.1109/ICECS.2008.4674971

A low jitter self-calibration PLL for 10Gbps SoC transmission links application

Kuo Hsing Cheng, Yu Chang Tsai, Kai Wei Hong, Yen Hsueh Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm².

Original language	English
Title of host publication	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages	786-789
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2008.4674971
State	Published - 2008
Event	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta Duration: 31 Aug 2008 → 3 Sep 2008

Publication series

Name	Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference	15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/Territory	Malta
City	St. Julian's
Period	31/08/08 → 3/09/08

Access to Document

10.1109/ICECS.2008.4674971

Cite this

Cheng, K. H., Tsai, Y. C., Hong, K. W., & Wu, Y. H. (2008). A low jitter self-calibration PLL for 10Gbps SoC transmission links application. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 786-789). Article 4674971 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4674971

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title = "A low jitter self-calibration PLL for 10Gbps SoC transmission links application",

abstract = "A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm2.",

author = "Cheng, {Kuo Hsing} and Tsai, {Yu Chang} and Hong, {Kai Wei} and Wu, {Yen Hsueh}",

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Cheng, KH, Tsai, YC, Hong, KW & Wu, YH 2008, A low jitter self-calibration PLL for 10Gbps SoC transmission links application. in Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4674971, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, pp. 786-789, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, Malta, 31/08/08. https://doi.org/10.1109/ICECS.2008.4674971

A low jitter self-calibration PLL for 10Gbps SoC transmission links application. / Cheng, Kuo Hsing; Tsai, Yu Chang; Hong, Kai Wei et al.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 786-789 4674971 (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm2.

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Cheng KH, Tsai YC, Hong KW, Wu YH. A low jitter self-calibration PLL for 10Gbps SoC transmission links application. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 786-789. 4674971. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). doi: 10.1109/ICECS.2008.4674971

A low jitter self-calibration PLL for 10Gbps SoC transmission links application

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