A low jitter self-calibration PLL for 10Gbps SoC transmission links application

Kuo Hsing Cheng, Yu Chang Tsai, Kai Wei Hong, Yen Hsueh Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small Kyco can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13μm CMOS technology. The PLL output jitter is 18.55ps (p-p) where the reference clock jitter is 20ps (p-p). The total power dissipation is 21mW at 2.5-GMz and the core area is 0.08mm2.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages786-789
Number of pages4
DOIs
StatePublished - 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sep 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/TerritoryMalta
CitySt. Julian's
Period31/08/083/09/08

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