A low jitter delay-locked-loop applied for DDR4

Keyphrases

• Delay-locked Loop 100%
• Low Jitter 100%
• DDR4 100%
• Supply Voltage 66%
• Gbps 66%
• Synchronous Circuit 66%
• On chip 33%
• Operation Frequency 33%
• Dynamic Random Access Memory 33%
• CMOS Technology 33%
• Input Frequency 33%
• Power Dissipation 33%
• Peak-to-peak Jitter 33%
• Chip Area 33%
• Charge Pump 33%
• RMS Jitter 33%
• Electronic Products 33%
• Current Matching 33%
• Supply Regulator 33%

Engineering

• Locked Loop 100%
• Supply Voltage 66%
• Frequency Operation 33%
• Dynamic Random Access Memory 33%
• Energy Dissipation 33%
• Input Frequency 33%
• Data Rate 33%
• Chip Area 33%
• Charge Pump 33%
• Electronic Product 33%