A low jitter delay-locked-loop applied for DDR4

Yo Hao Tu, Kuo Hsing Cheng, Hsiang Yun Wei, Hong Yi Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

This work is the demand for a stable and low-jitter synchronous circuit on intra-chip. The operation frequencies of electronic products constantly increase along with the de-velopment and breakthrough of the CMOS process technology. The complexity of design and frequency of clock in memory has also been rapidly increasing. Thus, the reliability of synchronous circuits becomes more and more essential. Dynamic Random Access Memory (DRAM) has progressed to DDR4, reaches data rate 1.6 Gbps - 3.2 Gbps. The stability of clock becomes an essential part of design. This work presents a technique that includes a current-matching charge pump and an on-chip supply regulator in the delay-locked loop (DLL). The design is implemented by TSMC CMOS 1P/9M 90 nm technology with a nominal supply voltage 1.2 V and I/O supply voltage 2.5 V. The input frequency is at 1.6 GHz. Peak to peak jitter is 12.33 ps and RMS jitter is 1.66 ps. The power dissipation of DLL is 15.6 mW and chip area is 0.047 mm2.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
PublisherIEEE Computer Society
Pages98-101
Number of pages4
ISBN (Print)9781467361361
DOIs
StatePublished - 2013
Event2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013 - Karlovy Vary, Czech Republic
Duration: 8 Apr 201310 Apr 2013

Publication series

NameProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013

Conference

Conference2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
Country/TerritoryCzech Republic
CityKarlovy Vary
Period8/04/1310/04/13

Keywords

  • charge pump (CP)
  • current mismatch
  • delay-locked loop (DLL)
  • double data rate (DDR)
  • low drop regulator (LDO)

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