A low-cost pipelined BIST scheme for homogeneous RAMs in multicore chips

Yu Jen Huang, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include a large amount of homogeneous memory cores (i.e., memory cores have the same size and configuration). This paper proposes a pipelined built-in self-test (PBIST) scheme for homogeneous memory cores in multicore SOCs. A PBIST circuit can be shared by clustered multiple homogeneous memories. This drastically reduces the hardware overhead of the PBIST circuit. A systematic procedure for converting a march test into a pipelined march test is also proposed. Experimental results show that the area overhead of a pipelined BIST for eight homogeneous 1k×128-bit memories is only about 0.71%.

Original languageEnglish
Title of host publicationProceedings of the 17th Asian Test Symposium, ATS 2008
Number of pages6
StatePublished - 2008
Event17th Asian Test Symposium, ATS 2008 - Sapporo, Japan
Duration: 24 Nov 200827 Nov 2008

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference17th Asian Test Symposium, ATS 2008


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