A low-cost Built-in Self-Test scheme for an array of memories

Yu Jen Huang, Che Wei Chou, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Modern processor and computation-intensive chips typically use the design style of multi-core chip architecture with identical logic and memory cores. Although memory built-in self-test (BIST) is a mature technique for testing embedded memories, testing multiple small memories using small area cost is still a challenge. This paper proposes a low area-cost BIST scheme for an array of memories and interconnections between memory cores and logic cores. To reduce the area cost without incurring long testing time, the BIST scheme tests multiple identical memories in a pipeline and each memory with a serial test interface. Experimental results show that the proposed BIST scheme has small area cost. For example, the proposed BIST scheme for 16 1024×64-bit RAMs only needs about 0.89% hardware over head.

Original languageEnglish
Title of host publication2010 15th IEEE European Test Symposium, ETS'10
Pages75-80
Number of pages6
DOIs
StatePublished - 2010
Event2010 15th IEEE European Test Symposium, ETS'10 - Prague, Czech Republic
Duration: 24 May 201028 May 2010

Publication series

Name2010 15th IEEE European Test Symposium, ETS'10

Conference

Conference2010 15th IEEE European Test Symposium, ETS'10
Country/TerritoryCzech Republic
CityPrague
Period24/05/1028/05/10

Fingerprint

Dive into the research topics of 'A low-cost Built-in Self-Test scheme for an array of memories'. Together they form a unique fingerprint.

Cite this