@inproceedings{e20e3ac8a20d4328b2257d5d6aa8991b,
title = "A low-cost and scalable test architecture for multi-core chips",
abstract = "Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core.",
keywords = "Array testing, Diagnosis, Multi-core, Scalable test architecture, Test, Test access mechanism",
author = "Chi, {Chun Chuan} and Wu, {Cheng Wen} and Li, {Jin Fu}",
year = "2010",
doi = "10.1109/ETSYM.2010.5512784",
language = "???core.languages.en_GB???",
isbn = "9781424458356",
series = "2010 15th IEEE European Test Symposium, ETS'10",
pages = "30--35",
booktitle = "2010 15th IEEE European Test Symposium, ETS'10",
note = "2010 15th IEEE European Test Symposium, ETS'10 ; Conference date: 24-05-2010 Through 28-05-2010",
}