A low-cost and scalable test architecture for multi-core chips

Chun Chuan Chi, Cheng Wen Wu, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Multi-core architecture has become a mainstream in modern processor and computation-intensive chips. A widely-used multi-core architecture contains identical cores. This paper proposes a low-cost and scalable test architecture for a multi-core chip with identical cores. The test architecture provides test scalability by using a two-dimensional pipelined test access mechanism (TAM). Also, some scan cells of the cores under test are reused as the pipeline registers of the TAM such that the area cost of the proposed test architecture is low. Experimental results show that the proposed test architecture only consumes about 2.6% area for a multi-core chip with 16 Advanced Encryption Standard (AES) cores. Also, the test time for 16 AES cores is only about 1.004 times of that for a single AES core.

Original languageEnglish
Title of host publication2010 15th IEEE European Test Symposium, ETS'10
Pages30-35
Number of pages6
DOIs
StatePublished - 2010
Event2010 15th IEEE European Test Symposium, ETS'10 - Prague, Czech Republic
Duration: 24 May 201028 May 2010

Publication series

Name2010 15th IEEE European Test Symposium, ETS'10

Conference

Conference2010 15th IEEE European Test Symposium, ETS'10
Country/TerritoryCzech Republic
CityPrague
Period24/05/1028/05/10

Keywords

  • Array testing
  • Diagnosis
  • Multi-core
  • Scalable test architecture
  • Test
  • Test access mechanism

Fingerprint

Dive into the research topics of 'A low-cost and scalable test architecture for multi-core chips'. Together they form a unique fingerprint.

Cite this