A Low-Complexity Generalized Memory Addressing Scheme for Continuous-Flow Fast Fourier Transform

Syu Siang Long, Meng Yao Hong, Muh Tian Shiue

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, a control logic-reduced memory addressing scheme with a modified arithmetic processing unit (PE) for memory-based fast Fourier transform (FFT) is presented. The proposed scheme supports the conflict-free memory accessing and continuous-flow (CF) FFT operation. Furthermore, the timing delay is independent of FFT length and the circuit area is minimized in the proposed address generator. A case study of radix-4 256-point CF-FFT is analyzed. The comparison results synthesized with 90nm CMOS technology show that the hardware complexity is significantly reduced. Therefore, the proposed addressing scheme is suitable for high radix algorithm and long FFT length applications.

Original languageEnglish
Title of host publication2018 3rd International Conference on Computer and Communication Systems, ICCCS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages502-505
Number of pages4
ISBN (Print)9781538663509
DOIs
StatePublished - 11 Sep 2018
Event3rd International Conference on Computer and Communication Systems, ICCCS 2018 - Nagoya, Japan
Duration: 27 Apr 201830 Apr 2018

Publication series

Name2018 3rd International Conference on Computer and Communication Systems, ICCCS 2018

Conference

Conference3rd International Conference on Computer and Communication Systems, ICCCS 2018
Country/TerritoryJapan
CityNagoya
Period27/04/1830/04/18

Keywords

  • conflict-free
  • continuous-flow
  • fast fourier transform
  • in-place
  • memory-based

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