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Abstract
In this paper, a control logic-reduced memory addressing scheme with a modified arithmetic processing unit (PE) for memory-based fast Fourier transform (FFT) is presented. The proposed scheme supports the conflict-free memory accessing and continuous-flow (CF) FFT operation. Furthermore, the timing delay is independent of FFT length and the circuit area is minimized in the proposed address generator. A case study of radix-4 256-point CF-FFT is analyzed. The comparison results synthesized with 90nm CMOS technology show that the hardware complexity is significantly reduced. Therefore, the proposed addressing scheme is suitable for high radix algorithm and long FFT length applications.
Original language | English |
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Title of host publication | 2018 3rd International Conference on Computer and Communication Systems, ICCCS 2018 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 502-505 |
Number of pages | 4 |
ISBN (Print) | 9781538663509 |
DOIs | |
State | Published - 11 Sep 2018 |
Event | 3rd International Conference on Computer and Communication Systems, ICCCS 2018 - Nagoya, Japan Duration: 27 Apr 2018 → 30 Apr 2018 |
Publication series
Name | 2018 3rd International Conference on Computer and Communication Systems, ICCCS 2018 |
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Conference
Conference | 3rd International Conference on Computer and Communication Systems, ICCCS 2018 |
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Country/Territory | Japan |
City | Nagoya |
Period | 27/04/18 → 30/04/18 |
Keywords
- conflict-free
- continuous-flow
- fast fourier transform
- in-place
- memory-based
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- 1 Finished
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Digital Baseband Design for Ieee Std 802.3bp?-2016 Next Generation Gigabit Ethernet Transmission( I )
Shiue, M.-T. (PI)
1/08/17 → 31/07/18
Project: Research