A logical fault model for library coherence checking

Shing W.U. Tung, Jing Yang Jou

Research output: Contribution to journalArticlepeer-review

7 Scopus citations


A library is the basis of modularized design flow. Most operations of CAD tools are based on cell definitions in a library. In this paper, we first give a definition of a library and describe the complexity of library verification. A unified automatic test pattern generation and verification environment is then proposed. The amount of library data coherence checking is reduced to functional simulation on different views of the cells. In order to reduce the number of test vectors and the amount of simulation lime, a Port Order Fault (POF) model is proposed. Using the POF model and the sensitized path approach [1] to generate test vectors, the proposed approach could effectively reduce the complexity of the functional test vectors from O(2″) to O(n) for cells with n inputs. Using the POF model, the test sequence can also detect timing inconsistency under the verification environment .

Original languageEnglish
Pages (from-to)567-586
Number of pages20
JournalJournal of Information Science and Engineering
Issue number3
StatePublished - Sep 1998


  • Cell Library
  • Coherence Checking
  • Fault Model
  • Port Order Fault (POF)
  • Test Pattern Generation
  • Verification


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