A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yun Chao Yu; Chih Sheng Hou; Li Jung Chang; Jin Fu Li; Chih Yen Lo; Ding Ming Kwai; Yung Fa Chou; Cheng Wen Wu

doi:10.1109/VTS.2013.6548927

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

Yun Chao Yu, Chih Sheng Hou, Li Jung Chang, Jin Fu Li, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

Original language	English
Title of host publication	Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013
DOIs	https://doi.org/10.1109/VTS.2013.6548927
State	Published - 2013
Event	2013 IEEE 31st VLSI Test Symposium, VTS 2013 - Berkeley, CA, United States Duration: 29 Apr 2013 → 1 May 2013

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium

Conference

Conference	2013 IEEE 31st VLSI Test Symposium, VTS 2013
Country/Territory	United States
City	Berkeley, CA
Period	29/04/13 → 1/05/13

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10.1109/VTS.2013.6548927

Cite this

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title = "A hybrid ECC and redundancy technique for reducing refresh power of DRAMs",

abstract = "Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.",

author = "Yu, {Yun Chao} and Hou, {Chih Sheng} and Chang, {Li Jung} and Li, {Jin Fu} and Lo, {Chih Yen} and Kwai, {Ding Ming} and Chou, {Yung Fa} and Wu, {Cheng Wen}",

year = "2013",

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language = "???core.languages.en_GB???",

isbn = "9781467355438",

series = "Proceedings of the IEEE VLSI Test Symposium",

booktitle = "Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013",

note = "2013 IEEE 31st VLSI Test Symposium, VTS 2013 ; Conference date: 29-04-2013 Through 01-05-2013",

}

Yu, YC, Hou, CS, Chang, LJ, Li, JF, Lo, CY, Kwai, DM, Chou, YF & Wu, CW 2013, A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. in Proceedings - 2013 IEEE 31st VLSI Test Symposium, VTS 2013., 6548927, Proceedings of the IEEE VLSI Test Symposium, 2013 IEEE 31st VLSI Test Symposium, VTS 2013, Berkeley, CA, United States, 29/04/13. https://doi.org/10.1109/VTS.2013.6548927

TY - GEN

T1 - A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

AU - Yu, Yun Chao

AU - Hou, Chih Sheng

AU - Chang, Li Jung

AU - Li, Jin Fu

AU - Lo, Chih Yen

AU - Kwai, Ding Ming

AU - Chou, Yung Fa

AU - Wu, Cheng Wen

PY - 2013

Y1 - 2013

N2 - Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

AB - Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem (BCH) module and an error-bit repair (EBR) module to raise the error correction capability and minimize the adverse effects caused by the ECC technique such that the refresh period can be effectively prolonged and considerable refresh power reduction can be achieved. Analysis results show that the proposed HEAR scheme can achieve 40∼70% of energy saving for a 2Gb DDR3 DRAM in standby mode. The area cost of parity data and ECC circuit of HEAR scheme is only about 63 % and 53 % of that of the ECC-only, respectively.

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T2 - 2013 IEEE 31st VLSI Test Symposium, VTS 2013

Y2 - 29 April 2013 through 1 May 2013

ER -

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs

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