A hybrid CAVLD architecture design with low complexity and low power considerations

Tsung Han Tsa; De Lung Fang; Yu Nan Pan

doi:10.1109/icme.2007.4285049

A hybrid CAVLD architecture design with low complexity and low power considerations

Tsung Han Tsa, De Lung Fang, Yu Nan Pan

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

In this paper, we proposed a hybrid high performance VLSI architecture for .MPEG-4 AVC/H.264 CAVLC decoding. We introduce two techniques to improve throughput of CAVLC decoder, which is called MSLD (Multi Symbol for Level Decoding) and NZS (Non Zero Skip for run_before decoding). Our proposed design can decode two levels and more than two run_befores in the same clock cycle. These two techniques have the advantages of low complexity and regularity design. According to the evaluation, our proposed design needs 137 cycles in average for one macroblock decoding. It says that this CAVLC decoder can run at 33.5 MHz to meet the real time requirement for H.264 video decoding on 1920×1088 resolution. Compared with the previous design, it can reduce around 56% work frequency for the same application. With a low working frequency, it will be suitable for a low power application.

Original language	English
Title of host publication	Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007
Publisher	IEEE Computer Society
Pages	1910-1913
Number of pages	4
ISBN (Print)	1424410177, 9781424410170
DOIs	https://doi.org/10.1109/icme.2007.4285049
State	Published - 2007
Event	IEEE International Conference onMultimedia and Expo, ICME 2007 - Beijing, China Duration: 2 Jul 2007 → 5 Jul 2007

Publication series

Name	Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007

Conference

Conference	IEEE International Conference onMultimedia and Expo, ICME 2007
Country/Territory	China
City	Beijing
Period	2/07/07 → 5/07/07

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10.1109/icme.2007.4285049

Cite this

Tsa, T. H., Fang, D. L., & Pan, Y. N. (2007). A hybrid CAVLD architecture design with low complexity and low power considerations. In Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 (pp. 1910-1913). Article 4285049 (Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007). IEEE Computer Society. https://doi.org/10.1109/icme.2007.4285049

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Tsa, TH, Fang, DL & Pan, YN 2007, A hybrid CAVLD architecture design with low complexity and low power considerations. in Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007., 4285049, Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, IEEE Computer Society, pp. 1910-1913, IEEE International Conference onMultimedia and Expo, ICME 2007, Beijing, China, 2/07/07. https://doi.org/10.1109/icme.2007.4285049

A hybrid CAVLD architecture design with low complexity and low power considerations. / Tsa, Tsung Han; Fang, De Lung; Pan, Yu Nan.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007. IEEE Computer Society, 2007. p. 1910-1913 4285049 (Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Tsa TH, Fang DL, Pan YN. A hybrid CAVLD architecture design with low complexity and low power considerations. In Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007. IEEE Computer Society. 2007. p. 1910-1913. 4285049. (Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007). doi: 10.1109/icme.2007.4285049

A hybrid CAVLD architecture design with low complexity and low power considerations

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