In this paper, we proposed a hybrid high performance VLSI architecture for .MPEG-4 AVC/H.264 CAVLC decoding. We introduce two techniques to improve throughput of CAVLC decoder, which is called MSLD (Multi Symbol for Level Decoding) and NZS (Non Zero Skip for run_before decoding). Our proposed design can decode two levels and more than two run_befores in the same clock cycle. These two techniques have the advantages of low complexity and regularity design. According to the evaluation, our proposed design needs 137 cycles in average for one macroblock decoding. It says that this CAVLC decoder can run at 33.5 MHz to meet the real time requirement for H.264 video decoding on 1920×1088 resolution. Compared with the previous design, it can reduce around 56% work frequency for the same application. With a low working frequency, it will be suitable for a low power application.