A hybrid built-in self-test scheme for DRAMs

Chi Chun Yang; Jin Fu Li; Yun Chao Yu; Kuan Te Wu; Chih Yen Lo; Chao Hsun Chen; Jenn Shiang Lai; Ding Ming Kwai; Yung Fa Chou

doi:10.1109/VLSI-DAT.2015.7114502

A hybrid built-in self-test scheme for DRAMs

Chi Chun Yang, Jin Fu Li, Yun Chao Yu, Kuan Te Wu, Chih Yen Lo, Chao Hsun Chen, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

Original language	English
Title of host publication	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479962754
DOIs	https://doi.org/10.1109/VLSI-DAT.2015.7114502
State	Published - 28 May 2015
Event	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 - Hsinchu, Taiwan Duration: 27 Apr 2015 → 29 Apr 2015

Publication series

Name	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Conference

Conference	2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015
Country/Territory	Taiwan
City	Hsinchu
Period	27/04/15 → 29/04/15

Access to Document

10.1109/VLSI-DAT.2015.7114502

Cite this

Yang, C. C., Li, J. F., Yu, Y. C., Wu, K. T., Lo, C. Y., Chen, C. H., Lai, J. S., Kwai, D. M., & Chou, Y. F. (2015). A hybrid built-in self-test scheme for DRAMs. In 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 Article 7114502 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2015.7114502

@inproceedings{5477a45043624625950a71b7698bed5d,

title = "A hybrid built-in self-test scheme for DRAMs",

abstract = "This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.",

author = "Yang, {Chi Chun} and Li, {Jin Fu} and Yu, {Yun Chao} and Wu, {Kuan Te} and Lo, {Chih Yen} and Chen, {Chao Hsun} and Lai, {Jenn Shiang} and Kwai, {Ding Ming} and Chou, {Yung Fa}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015 ; Conference date: 27-04-2015 Through 29-04-2015",

year = "2015",

month = may,

day = "28",

doi = "10.1109/VLSI-DAT.2015.7114502",

language = "???core.languages.en_GB???",

series = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015",

}

Yang, CC, Li, JF, Yu, YC, Wu, KT, Lo, CY, Chen, CH, Lai, JS, Kwai, DM & Chou, YF 2015, A hybrid built-in self-test scheme for DRAMs. in 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015., 7114502, 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Institute of Electrical and Electronics Engineers Inc., 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, 27/04/15. https://doi.org/10.1109/VLSI-DAT.2015.7114502

A hybrid built-in self-test scheme for DRAMs. / Yang, Chi Chun; Li, Jin Fu; Yu, Yun Chao et al.
2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7114502 (2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A hybrid built-in self-test scheme for DRAMs

AU - Yang, Chi Chun

AU - Li, Jin Fu

AU - Yu, Yun Chao

AU - Wu, Kuan Te

AU - Lo, Chih Yen

AU - Chen, Chao Hsun

AU - Lai, Jenn Shiang

AU - Kwai, Ding Ming

AU - Chou, Yung Fa

PY - 2015/5/28

Y1 - 2015/5/28

N2 - This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

AB - This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change the supported test algorithms. Simulation results show that the hybrid BIST only needs about 9553 gates to support march and non-march test algorithms for JEDEC WideIO DRAMs.

UR - http://www.scopus.com/inward/record.url?scp=84936970631&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2015.7114502

DO - 10.1109/VLSI-DAT.2015.7114502

M3 - 會議論文篇章

AN - SCOPUS:84936970631

T3 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

BT - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2015

Y2 - 27 April 2015 through 29 April 2015

ER -

A hybrid built-in self-test scheme for DRAMs

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