A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

Kuo Hsing Cheng, Cia Wei Su, Kai Fei Chang, Cheng Liang Hung, Wei Bin Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

Original languageEnglish
Title of host publicationESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Pages178-181
Number of pages4
DOIs
StatePublished - 2006
EventESSCIRC 2006 - 32nd European Solid-State Circuits Conference - Montreux, Switzerland
Duration: 19 Sep 200621 Sep 2006

Publication series

NameESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Country/TerritorySwitzerland
CityMontreux
Period19/09/0621/09/06

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