A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

Kuo Hsing Cheng; Cia Wei Su; Kai Fei Chang; Cheng Liang Hung; Wei Bin Yang

doi:10.1109/ESSCIR.2006.307560

A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

Kuo Hsing Cheng, Cia Wei Su, Kai Fei Chang, Cheng Liang Hung, Wei Bin Yang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

Original language	English
Title of host publication	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
Pages	178-181
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIR.2006.307560
State	Published - 2006
Event	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference - Montreux, Switzerland Duration: 19 Sep 2006 → 21 Sep 2006

Publication series

Name	ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

Conference

Conference	ESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Country/Territory	Switzerland
City	Montreux
Period	19/09/06 → 21/09/06

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10.1109/ESSCIR.2006.307560

Cite this

Cheng, K. H., Su, C. W., Chang, K. F., Hung, C. L., & Yang, W. B. (2006). A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference (pp. 178-181). Article 4099733 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIR.2006.307560

@inproceedings{15b28e54765848a8870a43e4b87bce73,

title = "A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation",

abstract = "In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.",

author = "Cheng, {Kuo Hsing} and Su, {Cia Wei} and Chang, {Kai Fei} and Hung, {Cheng Liang} and Yang, {Wei Bin}",

year = "2006",

doi = "10.1109/ESSCIR.2006.307560",

language = "???core.languages.en_GB???",

isbn = "1424403022",

series = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

pages = "178--181",

booktitle = "ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference",

note = "ESSCIRC 2006 - 32nd European Solid-State Circuits Conference ; Conference date: 19-09-2006 Through 21-09-2006",

}

Cheng, KH, Su, CW, Chang, KF, Hung, CL & Yang, WB 2006, A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. in ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference., 4099733, ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference, pp. 178-181, ESSCIRC 2006 - 32nd European Solid-State Circuits Conference, Montreux, Switzerland, 19/09/06. https://doi.org/10.1109/ESSCIR.2006.307560

A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. / Cheng, Kuo Hsing; Su, Cia Wei; Chang, Kai Fei et al.
ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. p. 178-181 4099733 (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

AU - Cheng, Kuo Hsing

AU - Su, Cia Wei

AU - Chang, Kai Fei

AU - Hung, Cheng Liang

AU - Yang, Wei Bin

PY - 2006

Y1 - 2006

N2 - In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

AB - In this paper, a high linearity PWCL is proposed. By using the linear control stage and digital-controlled charge pump (DCCP), the proposed PWCL can be operated in wide range of input duty cycle and produced wide range of output duty cycle in wide frequency range. Utilizing simple detect circuit to control DCCP in complementary architecture, the proposed PWCL can reduce lock time ratio to 4.9. The test chip was fabricated in 0.18μm CMOS process. The measurement results show that the frequency range of input signal is from 50MHz to 1.3GHz, the duty cycle range of input signal is from 30% to 70% and the programmable duty cycle of output signal is from 30% to 70% in steps of 5%. The measurement power dissipation and the peak-to-peak jitter are 4.8mW and 13.2ps respectively at an operation frequency of 1.3GHz.

UR - http://www.scopus.com/inward/record.url?scp=51749094362&partnerID=8YFLogxK

U2 - 10.1109/ESSCIR.2006.307560

DO - 10.1109/ESSCIR.2006.307560

M3 - 會議論文篇章

AN - SCOPUS:51749094362

SN - 1424403022

SN - 9781424403028

T3 - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

SP - 178

EP - 181

BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference

T2 - ESSCIRC 2006 - 32nd European Solid-State Circuits Conference

Y2 - 19 September 2006 through 21 September 2006

ER -

Cheng KH, Su CW, Chang KF, Hung CL, Yang WB. A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation. In ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference. 2006. p. 178-181. 4099733. (ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference). doi: 10.1109/ESSCIR.2006.307560

A high linearity and fast-locked pulse width control loop with digitally programmable output duty cycle for wide range operation

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