A hierarchical test methodology for systems on chip

Jin Fu Li; Hsin Jung Huang; Jeng Bin Chen; Chih Pin Su; Cheng Wen Wu; Chuang Cheng; Shao I. Chen; Chi Yi Hwang; Hsiao Ping Lin

doi:10.1109/MM.2002.1044301

A hierarchical test methodology for systems on chip

Jin Fu Li, Hsin Jung Huang, Jeng Bin Chen, Chih Pin Su, Cheng Wen Wu, Chuang Cheng, Shao I. Chen, Chi Yi Hwang, Hsiao Ping Lin

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Original language	English
Pages (from-to)	69-81
Number of pages	13
Journal	IEEE Micro
Volume	22
Issue number	5
DOIs	https://doi.org/10.1109/MM.2002.1044301
State	Published - Sep 2002

Access to Document

10.1109/MM.2002.1044301

Cite this

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title = "A hierarchical test methodology for systems on chip",

author = "Li, {Jin Fu} and Huang, {Hsin Jung} and Chen, {Jeng Bin} and Su, {Chih Pin} and Wu, {Cheng Wen} and Chuang Cheng and Chen, {Shao I.} and Hwang, {Chi Yi} and Lin, {Hsiao Ping}",

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T1 - A hierarchical test methodology for systems on chip

AU - Li, Jin Fu

AU - Huang, Hsin Jung

AU - Chen, Jeng Bin

AU - Su, Chih Pin

AU - Wu, Cheng Wen

AU - Cheng, Chuang

AU - Chen, Shao I.

AU - Hwang, Chi Yi

AU - Lin, Hsiao Ping

PY - 2002/9

Y1 - 2002/9

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U2 - 10.1109/MM.2002.1044301

DO - 10.1109/MM.2002.1044301

M3 - 期刊論文

AN - SCOPUS:0036760593

SN - 0272-1732

VL - 22

SP - 69

EP - 81

JO - IEEE Micro

JF - IEEE Micro

IS - 5

ER -