A hardware efficient 64-QAM low-IF transceiver baseband for broadband communications

Ching Chi Chang, Muh Tian Shiue, Chorng Kuang Wang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a hardware efficient VLSI design of digital baseband for 64-QAM communication systems over the last-mile cable network. This VLSI system design involves a cost-efficient architecture of the adaptive equalizer and a two-phase linear architecture of the pulse shaping filters, which reduce the hardware requirement by a factor of four comparing with traditional quadrature direct form FIR filters. In this design, the two-fold carrier recovery loop possesses a pull-in range of ±100kHz (i.e. ±18, 500ppm of the symbol rate) and -82dBc jitter suppression. Based on the proposed multi-staged LMS-based fractionally-spaced equalizer, the receiver realizes the symbol spaced timing recovery in a ±200ppm tolerance of the symbol rate. The acquisition time of the proposed 64-QAM blind adaptive system is 7ms, and the transceiver reaches the operation speed of the case for 32.28Mb/s 64-QAM low-IF digital CATV system over NTSC 6MHz bandwidth channels. Using 0.35μm CMOS technology, the transceiver design occupies a chip area 5.5mm × 5.5mm and power consumption 1.35W (1.0W for RX) when the power supply is 3.3V.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages252-255
Number of pages4
StatePublished - 2004
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 4 Aug 20045 Aug 2004

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Country/TerritoryJapan
CityFukuoka
Period4/08/045/08/04

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