A formal method to improve SystemVerilog functional coverage

An Che Cheng, Chia Chih Yen, Jing Yang Jou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce deterministic test patterns for complete coverage. The framework is based on the functional coverage model (covergroup) provided by SystemVerilog, and it could be easily integrated to modern digital design flow. We synthesize a practical subset of covergroup language constructs to enable FTPG by a SAT-solver. An algorithm called MRRS is proposed to minimize the potential large complexity of the synthesized circuits. Preliminary experimental results demonstrate that MRRS could facilitate FTPG to achieve 43X speed-up in average while the maximum speed-up can reach 67X. To the best of our knowledge, this is the first paper which proposes an FTPG method that utilizes covergroups.

Original languageEnglish
Title of host publication2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012
Pages56-63
Number of pages8
DOIs
StatePublished - 2012
Event2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012 - Huntington Beach, CA, United States
Duration: 9 Nov 201210 Nov 2012

Publication series

NameProceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT
ISSN (Print)1552-6674

Conference

Conference2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012
Country/TerritoryUnited States
CityHuntington Beach, CA
Period9/11/1210/11/12

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