This paper describes a fast-lock delay-lock loop (DLL) with power-on reset (FOR) circuit. The FOR circuit and coarse tune (CT) circuit are proposed to overcome the problems of the false locking associated with conventional DLL's and offer the faster locking time. Moreover, the proposed VCDL can reduce dynamic switching power dissipation and noise. The chip is fabricated in a 0.35μm CMOS process. From the measurement results, the DLL can operate correctly from 100 to190MHz and generate equally spaced eight-phase clocks. When the input clock frequency is 100MHz, the measured output clock peak-to-peak jitter and rms jitter are 56ps and 12.44ps, respectively. And when the input clock frequency is 190MHz, the measured output clock peak-to-peak jitter and rms jitter are 46ps and 8.463ps, respectively. Besides, the maximum lock time is 43 clock cycles at 150MHz.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2004|
|Event||2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 23 May 2004 → 26 May 2004