A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop

Kuo Hsing Cheng, Wei Bin Yang, Cheng Ming Ying

Research output: Contribution to journalArticlepeer-review

37 Scopus citations

Abstract

In this paper, a dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A coarse-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed phased-locked loop (PLL) circuit is designed based on the TSMC 0.35-μm 1P4M CMOS process with a 3.3-V supply voltage. HSPICE simulation show s that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurement results show that the proposed PLL has fast locking properties.

Original languageEnglish
Pages (from-to)892-896
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume50
Issue number11
DOIs
StatePublished - Nov 2003

Keywords

  • Coarse-tuning loop
  • Dual-slope
  • Fast locking
  • Fine-tuning loop
  • Phased-locked loop (PLL)

Fingerprint

Dive into the research topics of 'A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop'. Together they form a unique fingerprint.

Cite this