In this paper, a dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loops is proposed and analyzed. The proposed topology is based on two tuning loops: a fine-tuning loop and a coarse-tuning loop. A coarse-tuning loop is used for fast convergence, and a fine-tuning loop is used to complete fine adjustments. The proposed PLL circuit is designed based on the TSMC 0.3 um 1P4M CMOS process with a 3.3V supply voltage. HSPICE simulation shows that the lock time of the proposed PLL can be reduced over 82% in comparison to the conventional PLL. An experimental chip was implemented and measured. The measurement results show that the proposed PLL has fast locking properties.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2004|
|Event||2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 23 May 2004 → 26 May 2004