Abstract
In this paper, a low voltage dual-pulse-clock double edge triggered D-flip-flop (DPDET) is proposed. The DPDET flip-flop uses a split output latch clocked by a short pulse train. Compared to the previously reported double edge triggered flip-flops, the DPDET flip-flop uses only six transistors with two transistors being clocked, operating correctly under low supply voltage. The total transistors count is reduced to improve speed and power dissipation in flip-flop. The number of transistors is reduced by 40% to 70% compared to other double edge triggered flip-flops. Based on 0.35 um single-poly quad-metal CMOS technology, the HSPICE simulation results show that the operating speed of the DPDET flip-flop is 2.7 GHz at a 3.3 V supply voltage. The operating speed of the DPDET flip-flop is increased about 41% and 49% in compared with others for 3.3 V and 2.5 V supply voltage, respectively. The power dissipation is reduced about 36% and 29% in compared with others for 3.3 V and 2.5 V supply voltage, respectively. Moreover, the DPDET flip-flop can be used in a 0.9 V supply voltage with 224 MHz operating speed. Therefore the proposed DPDET flip-flop is suitable for low supply voltage and high speed CMOS applications.
| Original language | English |
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| Pages (from-to) | V425-V428 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 5 |
| State | Published - 2003 |
| Event | Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003 |