A difference detector PFD for low jitter PLL

Kuo Hsing Cheng, Tse Hua Yao, Shu Yu Jiang, Wei Bin Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

33 Scopus citations

Abstract

For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6GHz. Furthermore, with difference detector, the dd-PFD has three-state, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16ps. The proposed PFD is designed using 0.35um CMOS technology at 3.3V power supply.

Original languageEnglish
Title of host publicationICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages43-46
Number of pages4
StatePublished - 2001
Event8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta
Duration: 2 Sep 20015 Sep 2001

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Conference

Conference8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/TerritoryMalta
Period2/09/015/09/01

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