A difference detector PFD for low jitter PLL

Kuo Hsing Cheng; Tse Hua Yao; Shu Yu Jiang; Wei Bin Yang

A difference detector PFD for low jitter PLL

Kuo Hsing Cheng, Tse Hua Yao, Shu Yu Jiang, Wei Bin Yang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

35 Scopus citations

Abstract

For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6GHz. Furthermore, with difference detector, the dd-PFD has three-state, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16ps. The proposed PFD is designed using 0.35um CMOS technology at 3.3V power supply.

Original language	English
Title of host publication	ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Pages	43-46
Number of pages	4
State	Published - 2001
Event	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 - , Malta Duration: 2 Sep 2001 → 5 Sep 2001

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	1

Conference

Conference	8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
Country/Territory	Malta
Period	2/09/01 → 5/09/01

Cite this

@inproceedings{3f0bf578f2a64234bd120810a9c12ec5,

title = "A difference detector PFD for low jitter PLL",

abstract = "For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6GHz. Furthermore, with difference detector, the dd-PFD has three-state, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16ps. The proposed PFD is designed using 0.35um CMOS technology at 3.3V power supply.",

author = "Cheng, {Kuo Hsing} and Yao, {Tse Hua} and Jiang, {Shu Yu} and Yang, {Wei Bin}",

year = "2001",

language = "???core.languages.en_GB???",

isbn = "0780370570",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

pages = "43--46",

booktitle = "ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems",

note = "8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001 ; Conference date: 02-09-2001 Through 05-09-2001",

}

Cheng, KH, Yao, TH, Jiang, SY & Yang, WB 2001, A difference detector PFD for low jitter PLL. in ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems., 957660, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, pp. 43-46, 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, 2/09/01.

A difference detector PFD for low jitter PLL. / Cheng, Kuo Hsing; Yao, Tse Hua; Jiang, Shu Yu et al.
ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems. 2001. p. 43-46 957660 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A difference detector PFD for low jitter PLL

AU - Cheng, Kuo Hsing

AU - Yao, Tse Hua

AU - Jiang, Shu Yu

AU - Yang, Wei Bin

PY - 2001

Y1 - 2001

N2 - For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6GHz. Furthermore, with difference detector, the dd-PFD has three-state, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16ps. The proposed PFD is designed using 0.35um CMOS technology at 3.3V power supply.

AB - For high speed and low jitter PLL application, a new phase frequency detector (PFD) with difference detector is proposed. Because the proposed difference detector PFD (dd-PFD) doesn't have any feedback path in phase frequency detector circuit, it can be operated up to 1.6GHz. Furthermore, with difference detector, the dd-PFD has three-state, so it will not have phase errors and jitter problems. The dead zone of dd-PFD is 16ps. The proposed PFD is designed using 0.35um CMOS technology at 3.3V power supply.

UR - http://www.scopus.com/inward/record.url?scp=67650001106&partnerID=8YFLogxK

M3 - 會議論文篇章

AN - SCOPUS:67650001106

SN - 0780370570

SN - 9780780370579

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

SP - 43

EP - 46

BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems

T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001

Y2 - 2 September 2001 through 5 September 2001

ER -

A difference detector PFD for low jitter PLL

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