A DFT for semi-DC fault diagnosis for switched-capacitor circuits

Sheng Jer Kuo, Chung Len Lee, Soon Jyh Chang, Jwu E. Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, a design-for testability (DFT) technique is presented to diagnose switched-capacitor (SC) circuits. In order to avoid the effect that pure DC signal cannot pass through un-switched capacitors, we use semi-DC signal to diagnose SC circuits. Furthermore, we propose a controllable opamp that it can be controlled to normal mode or test mode. In normal mode, it passes signal normally; in test mode, it provides a semi-DC test signal (VDD or VSS) and blocks the signals from the stage before controlled stage. In our diagnosis method, we consider faults both in capacitors and in opamps. Experiments have carried out to verify the practicality of this technique.

Original languageEnglish
Title of host publicationProceedings - European Test Workshop 1999, ETW 1999
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages58-63
Number of pages6
ISBN (Electronic)076950390X, 9780769503905
DOIs
StatePublished - 1999
Event1999 European Test Workshop, ETW 1999 - Constance, Germany
Duration: 25 May 199928 May 1999

Publication series

NameProceedings - European Test Workshop 1999, ETW 1999

Conference

Conference1999 European Test Workshop, ETW 1999
Country/TerritoryGermany
CityConstance
Period25/05/9928/05/99

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