A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability

Jin Fu Li, Jiunn Der Yu, Yu Jen Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

This paper presents a design methodology of reconfigurable hybrid carry lookahead/carry select adders (CLSAs). A novel partition scheme is used to divide a large hybrid CLSA into multiple small ones with blocking specific inputs of the carry lookahead unit in the hybrid CLSA. The partition scheme incurs no delay penalty regardless of the size of adders. Moreover, the additional area cost is very small. For example, a reconfigurable 16-bit hybrid CLSA with four different partition configurations needs additional 6 two-input AND gates and three two-input multiplexers. Simulation results show that the delay of a 64-bit reconfigurable CLSA is only about 1.38ns in 0.18μm technology.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages77-80
Number of pages4
ISBN (Print)9780780388345
DOIs
StatePublished - 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

ConferenceIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Country/TerritoryJapan
CityKobe
Period23/05/0526/05/05

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