A compiled-code parallel pattern logic simulator with inertial delay model

Kuo Chan Huang, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalArticlepeer-review


This paper presents a parallel pattern compiled code logic simulator which can handle the transport delay as well as the inertial delay of the logic gate, it uses Potential-Change Frame, incorporating inertial functions, to execute event-canceling operation of gates, thus eliminating the conventional time wheel mechanism. As a result, it can adopt the parallel pattern strategy to increase the simulation speed. Furthermore, it is a compiled code simulator, which further improves its performance. Experimental results show that it significantly surpasses the conventional time wheel event-driven simulator in terms of simulation speed. In addition, it is also found that a significant percentage (27%) of hazards can be eliminated when the effect of the inertial delay is considered in the simulation.

Original languageEnglish
Pages (from-to)885-897
Number of pages13
JournalJournal of Information Science and Engineering
Issue number6
StatePublished - Nov 1999


  • Compiled code simulation
  • Inertial delay model
  • Logic simulator
  • Parallel pattern
  • Potential change frame


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