A compact and low-power SRAM with improved read static noise margin

Cihun Siyong Alex Gong, Ci Tong Hong, Kai Wen Yao, Muh Tian Shiue, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An efficient static random access memory (SRAM) is presented in this paper. By using a newly developed architecture based on "preequalize" scheme, the geometry ratio between the pull-up and pull-down driver transistors of conventional 6-T cell will be similar to that of familiar inverter, thereby making the SRAM be provided with an improved read static noise margin (SNM) and a reduced cell area. The removal of DC path resulting from preequalize also yields significant power reduction. To avoid a write speed degradation caused by the internal race on cell current between the pull-up driver transistor and access transistor, a write-power-off scheme is proposed. To further decrease the write power consumption, data drivers are connected to the bit lines instead of the conventional power supply terminals. A 4-kb-capacity test prototype has been designed in a 0.18-μm CMOS process. Achievable power reduction for the proposed SRAM is approximately 16% according to the post-layout simulation results (with the parasitics extracted), compared to that designed in the conventional architecture.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages546-549
Number of pages4
DOIs
StatePublished - 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sep 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/TerritoryMalta
CitySt. Julian's
Period31/08/083/09/08

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