TY - GEN
T1 - A cocktail approach on random access scan toward low power and high efficiency test
AU - Lin, Shih Ping
AU - Lee, Chung Len
AU - Chen, Jwu E.
PY - 2005
Y1 - 2005
N2 - Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the Random Access Scan (RAS) scheme offers a solution to alleviate the above problems [6]. In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, Test Response Abundant, Constrained Static Compaction, and Bit Propagation Before Test Vector Dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.
AB - Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the Random Access Scan (RAS) scheme offers a solution to alleviate the above problems [6]. In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, Test Response Abundant, Constrained Static Compaction, and Bit Propagation Before Test Vector Dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.
UR - http://www.scopus.com/inward/record.url?scp=33751430492&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2005.1560046
DO - 10.1109/ICCAD.2005.1560046
M3 - 會議論文篇章
AN - SCOPUS:33751430492
SN - 078039254X
SN - 9780780392540
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 94
EP - 99
BT - Proceedings of theICCAD-2005
T2 - ICCAD-2005: IEEE/ACM International Conference on Computer-Aided Design, 2005
Y2 - 6 November 2005 through 10 November 2005
ER -