A CNN Accelerator on FPGA using Binary Weight Networks

Tsung Han Tsai, Yuan Chen Ho

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

At present, convolutional neural networks have good performance while performing the object recognition tasks, but it relies on GPUs to solve a large number of complex operations. Therefore, the hardware accelerator of the neural network has become a central topic in the hardware researchers. This letter presents the design of an FPGA-based neural network accelerator implemented on the Xilinx Zynq-7020 FPGA. We use the binary LeNet model to achieve 91% accuracy in the MNIST dataset and use binary AlexNet model to achieve 67% accuracy in the CIFAR-10 dataset. Meanwhile the hardware resource is only about 10% usage on FPGA of the original design.

Original languageEnglish
Title of host publication2020 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728173993
DOIs
StatePublished - 28 Sep 2020
Event7th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2020 - Taoyuan, Taiwan
Duration: 28 Sep 202030 Sep 2020

Publication series

Name2020 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2020

Conference

Conference7th IEEE International Conference on Consumer Electronics - Taiwan, ICCE-Taiwan 2020
Country/TerritoryTaiwan
CityTaoyuan
Period28/09/2030/09/20

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