A CMOS VCO for IV, 1GHz PLL applications

Kuo Hsing Cheng, Ching Wen Lai, Yu Lung Lo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

This paper describes a 1V, 1GHz low-noise phase locked- loop (PLL) using a noise-rejected voltage-controlled ring oscillator (VCO). In order to improve the power consumption and oscillation frequency of the PLL, we design the VCO with a new structure of the delay cell. This VCO consists of four-stage fully differential delay cells with the pre-charged scheme that can obtain the characteristics of high speed and low voltage operation. And the bias generator circuit can increase the tuning range and tuning linearity of VCO. The HSPICE simulation results are based upon TSMC 0.18μm 1P6M N-well CMOS process. The simulation results show that the VCO can operate from 50 to 1100 MHz, and when the input control voltage is 0.6V, the oscillation frequency is 1GHz. The power consumption of the PLL is 1.092mW at a supply voltage of 1V.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages150-153
Number of pages4
StatePublished - 2004
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 4 Aug 20045 Aug 2004

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Country/TerritoryJapan
CityFukuoka
Period4/08/045/08/04

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