A CMOS adaptive equalizer using low-voltage zero generators technique

Yu Chang Tsai; Kuo Hsing Cheng; Yen Hsueh Wu; Ying Fu Lin

doi:10.1109/ESSCIRC.2010.5619764

A CMOS adaptive equalizer using low-voltage zero generators technique

Yu Chang Tsai, Kuo Hsing Cheng, Yen Hsueh Wu, Ying Fu Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 mm² (including output buffers), and output peak-to-peak jitter is 0.28 UI. The equalizer achieves high frequency compensation, small area, and low power consumption.

Original language	English
Title of host publication	ESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages	546-549
Number of pages	4
DOIs	https://doi.org/10.1109/ESSCIRC.2010.5619764
State	Published - 2010
Event	36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain Duration: 14 Sep 2010 → 16 Sep 2010

Publication series

Name	ESSCIRC 2010 - 36th European Solid State Circuits Conference

Conference

Conference	36th European Solid State Circuits Conference, ESSCIRC 2010
Country/Territory	Spain
City	Sevilla
Period	14/09/10 → 16/09/10

Keywords

Adaptive equalizer
Equalizing filter
High-speed serial links
Inductorless
Power detector

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10.1109/ESSCIRC.2010.5619764

Cite this

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title = "A CMOS adaptive equalizer using low-voltage zero generators technique",

abstract = "This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 mm2 (including output buffers), and output peak-to-peak jitter is 0.28 UI. The equalizer achieves high frequency compensation, small area, and low power consumption.",

keywords = "Adaptive equalizer, Equalizing filter, High-speed serial links, Inductorless, Power detector",

author = "Tsai, {Yu Chang} and Cheng, {Kuo Hsing} and Wu, {Yen Hsueh} and Lin, {Ying Fu}",

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Tsai, YC, Cheng, KH, Wu, YH & Lin, YF 2010, A CMOS adaptive equalizer using low-voltage zero generators technique. in ESSCIRC 2010 - 36th European Solid State Circuits Conference., 5619764, ESSCIRC 2010 - 36th European Solid State Circuits Conference, pp. 546-549, 36th European Solid State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, 14/09/10. https://doi.org/10.1109/ESSCIRC.2010.5619764

A CMOS adaptive equalizer using low-voltage zero generators technique. / Tsai, Yu Chang; Cheng, Kuo Hsing; Wu, Yen Hsueh; Lin, Ying Fu.

ESSCIRC 2010 - 36th European Solid State Circuits Conference. 2010. p. 546-549 5619764 (ESSCIRC 2010 - 36th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Tsai, Yu Chang

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AU - Lin, Ying Fu

PY - 2010

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N2 - This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 mm2 (including output buffers), and output peak-to-peak jitter is 0.28 UI. The equalizer achieves high frequency compensation, small area, and low power consumption.

AB - This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 mm2 (including output buffers), and output peak-to-peak jitter is 0.28 UI. The equalizer achieves high frequency compensation, small area, and low power consumption.

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KW - Equalizing filter

KW - High-speed serial links

KW - Inductorless

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ER -

A CMOS adaptive equalizer using low-voltage zero generators technique

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Keywords

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