A CMOS adaptive equalizer using low-voltage zero generators technique

Yu Chang Tsai, Kuo Hsing Cheng, Yen Hsueh Wu, Ying Fu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a 5 Gb/s adaptive equalizer that compensates for the FR-4 channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency tunable gain boosting without inductors. The power detector combines current steering techniques and a pre-amplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6 V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 mm2 (including output buffers), and output peak-to-peak jitter is 0.28 UI. The equalizer achieves high frequency compensation, small area, and low power consumption.

Original languageEnglish
Title of host publicationESSCIRC 2010 - 36th European Solid State Circuits Conference
Pages546-549
Number of pages4
DOIs
StatePublished - 2010
Event36th European Solid State Circuits Conference, ESSCIRC 2010 - Sevilla, Spain
Duration: 14 Sep 201016 Sep 2010

Publication series

NameESSCIRC 2010 - 36th European Solid State Circuits Conference

Conference

Conference36th European Solid State Circuits Conference, ESSCIRC 2010
Country/TerritorySpain
CitySevilla
Period14/09/1016/09/10

Keywords

  • Adaptive equalizer
  • Equalizing filter
  • High-speed serial links
  • Inductorless
  • Power detector

Fingerprint

Dive into the research topics of 'A CMOS adaptive equalizer using low-voltage zero generators technique'. Together they form a unique fingerprint.

Cite this