A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

E. R. Hsieh, C. M. Hung, T. Y. Wang, Steve S. Chung, R. M. Huang, C. T. Tsai, T. R. Yew

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, Avt, Agm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.

Original languageEnglish
Title of host publication2014 IEEE International Electron Devices Meeting, IEDM 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages12.2.1-12.2.4
EditionFebruary
ISBN (Electronic)9781479980017
DOIs
StatePublished - 20 Feb 2015
Event2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
Duration: 15 Dec 201417 Dec 2014

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
NumberFebruary
Volume2015-February
ISSN (Print)0163-1918

Conference

Conference2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Country/TerritoryUnited States
CitySan Francisco
Period15/12/1417/12/14

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