A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

E. R. Hsieh; C. M. Hung; T. Y. Wang; Steve S. Chung; R. M. Huang; C. T. Tsai; T. R. Yew

doi:10.1109/IEDM.2014.7047036

A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

E. R. Hsieh, C. M. Hung, T. Y. Wang, Steve S. Chung, R. M. Huang, C. T. Tsai, T. R. Yew

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, A_vt, A_gm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.

Original language	English
Title of host publication	2014 IEEE International Electron Devices Meeting, IEDM 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	12.2.1-12.2.4
Edition	February
ISBN (Electronic)	9781479980017
DOIs	https://doi.org/10.1109/IEDM.2014.7047036
State	Published - 20 Feb 2015
Event	2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States Duration: 15 Dec 2014 → 17 Dec 2014

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Number	February
Volume	2015-February
ISSN (Print)	0163-1918

Conference

Conference	2014 60th IEEE International Electron Devices Meeting, IEDM 2014
Country/Territory	United States
City	San Francisco
Period	15/12/14 → 17/12/14

Access to Document

10.1109/IEDM.2014.7047036

Cite this

Hsieh, E. R., Hung, C. M., Wang, T. Y., Chung, S. S., Huang, R. M., Tsai, C. T., & Yew, T. R. (2015). A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology. In 2014 IEEE International Electron Devices Meeting, IEDM 2014 (February ed., pp. 12.2.1-12.2.4). [7047036] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2014.7047036

Hsieh, E. R. ; Hung, C. M. ; Wang, T. Y. et al. / A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology. 2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 12.2.1-12.2.4 (Technical Digest - International Electron Devices Meeting, IEDM; February).

@inproceedings{95dd737894c74d00808e0f573d8600b6,

title = "A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology",

abstract = "Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, Avt, Agm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.",

author = "Hsieh, {E. R.} and Hung, {C. M.} and Wang, {T. Y.} and Chung, {Steve S.} and Huang, {R. M.} and Tsai, {C. T.} and Yew, {T. R.}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 60th IEEE International Electron Devices Meeting, IEDM 2014 ; Conference date: 15-12-2014 Through 17-12-2014",

year = "2015",

month = feb,

day = "20",

doi = "10.1109/IEDM.2014.7047036",

language = "???core.languages.en_GB???",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "February",

pages = "12.2.1--12.2.4",

booktitle = "2014 IEEE International Electron Devices Meeting, IEDM 2014",

edition = "February",

}

Hsieh, ER, Hung, CM, Wang, TY, Chung, SS, Huang, RM, Tsai, CT & Yew, TR 2015, A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology. in 2014 IEEE International Electron Devices Meeting, IEDM 2014. February edn, 7047036, Technical Digest - International Electron Devices Meeting, IEDM, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 12.2.1-12.2.4, 2014 60th IEEE International Electron Devices Meeting, IEDM 2014, San Francisco, United States, 15/12/14. https://doi.org/10.1109/IEDM.2014.7047036

A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology. / Hsieh, E. R.; Hung, C. M.; Wang, T. Y. et al.
2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 12.2.1-12.2.4 7047036 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

AU - Hsieh, E. R.

AU - Hung, C. M.

AU - Wang, T. Y.

AU - Chung, Steve S.

AU - Huang, R. M.

AU - Tsai, C. T.

AU - Yew, T. R.

PY - 2015/2/20

Y1 - 2015/2/20

N2 - Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, Avt, Agm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.

AB - Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, Avt, Agm, in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.

UR - http://www.scopus.com/inward/record.url?scp=84938250775&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2014.7047036

DO - 10.1109/IEDM.2014.7047036

M3 - 會議論文篇章

AN - SCOPUS:84938250775

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 12.2.1-12.2.4

BT - 2014 IEEE International Electron Devices Meeting, IEDM 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 60th IEEE International Electron Devices Meeting, IEDM 2014

Y2 - 15 December 2014 through 17 December 2014

ER -

Hsieh ER, Hung CM, Wang TY, Chung SS, Huang RM, Tsai CT et al. A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology. In 2014 IEEE International Electron Devices Meeting, IEDM 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 12.2.1-12.2.4. 7047036. (Technical Digest - International Electron Devices Meeting, IEDM; February). doi: 10.1109/IEDM.2014.7047036

A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this