TY - GEN
T1 - A chopper stabilized front-end for neural recording applications with DC-drift suppressed amplifier
AU - Yao, Kai Wen
AU - Lin, Wei Chih
AU - Gong, Cihun Siyong Alex
AU - Tsai, Ming Chih
AU - Hsueh, Yu Ting
AU - Shiue, Muh Tian
PY - 2009
Y1 - 2009
N2 - A chopper stabilized front-end with an active dc-suppressed topology used to record extracellular neural action potentials and local field potentials is presented in this paper. An active dc-suppressed topology, such as a bandpass filter, containing an amplifier with an integrator on the feedback path, suppresses baseline drift and assures weak inversion operations of input stages of the proposed bandpass filter. Floating tunable resistors are also employed to produce large resistance, providing large time constant to reduce low frequency noise. The proposed front-end circuitry needs no external capacitors and resistors and adjusts highpass cutoff frequency arbitrarily by altering control voltage of floating tunable resistors. The work in this paper, designed in a 0.18-μm CMOS process, provides sufficiently high linearity at least 10-bit SNDR, a midband gain of 63 dB, and signal bandwidth of approximately 13 kHz. Supplied at 1.8 V, the proposed front-end consumes around 231 μW. With the proposed chopping technique, a total of 7.05-μVrms input-referred noise can be achieved at the signal bandwidth.
AB - A chopper stabilized front-end with an active dc-suppressed topology used to record extracellular neural action potentials and local field potentials is presented in this paper. An active dc-suppressed topology, such as a bandpass filter, containing an amplifier with an integrator on the feedback path, suppresses baseline drift and assures weak inversion operations of input stages of the proposed bandpass filter. Floating tunable resistors are also employed to produce large resistance, providing large time constant to reduce low frequency noise. The proposed front-end circuitry needs no external capacitors and resistors and adjusts highpass cutoff frequency arbitrarily by altering control voltage of floating tunable resistors. The work in this paper, designed in a 0.18-μm CMOS process, provides sufficiently high linearity at least 10-bit SNDR, a midband gain of 63 dB, and signal bandwidth of approximately 13 kHz. Supplied at 1.8 V, the proposed front-end consumes around 231 μW. With the proposed chopping technique, a total of 7.05-μVrms input-referred noise can be achieved at the signal bandwidth.
UR - http://www.scopus.com/inward/record.url?scp=77749306392&partnerID=8YFLogxK
U2 - 10.1109/BIOCAS.2009.5372081
DO - 10.1109/BIOCAS.2009.5372081
M3 - 會議論文篇章
AN - SCOPUS:77749306392
SN - 9781424449187
T3 - 2009 IEEE Biomedical Circuits and Systems Conference, BioCAS 2009
SP - 77
EP - 80
BT - 2009 IEEE Biomedical Circuits and Systems Conference, BioCAS 2009
T2 - 2009 IEEE Biomedical Circuits and Systems Conference, BioCAS 2009
Y2 - 26 November 2009 through 28 November 2009
ER -