A channel-sharable built-in self-test scheme for multi-channel DRAMs

Kuan Te Wu; Jin Fu Li; Chih Yen Lo; Jenn Shiang Lai; Ding Ming Kwai; Yung Fa Chou

doi:10.1109/ASPDAC.2018.8297313

A channel-sharable built-in self-test scheme for multi-channel DRAMs

Kuan Te Wu, Jin Fu Li, Chih Yen Lo, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

Original language	English
Title of host publication	ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	245-250
Number of pages	6
ISBN (Electronic)	9781509006021
DOIs	https://doi.org/10.1109/ASPDAC.2018.8297313
State	Published - 20 Feb 2018
Event	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of Duration: 22 Jan 2018 → 25 Jan 2018

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2018-January

Conference

Conference	23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Country/Territory	Korea, Republic of
City	Jeju
Period	22/01/18 → 25/01/18

Keywords

built-in self-test
channel-based DRAM
DRAM
March test
test

Access to Document

10.1109/ASPDAC.2018.8297313

Testing of Emerging Nonvolatile-Based Memories for Iot(2/3)
Li, J.
1/08/17 → 31/07/18
Project: Research
Testing and Reliability-Enhancement Techniques for Stacked Memories(2/3)
Li, J.
1/08/17 → 31/07/18
Project: Research

Cite this

Wu, K. T., Li, J. F., Lo, C. Y., Lai, J. S., Kwai, D. M., & Chou, Y. F. (2018). A channel-sharable built-in self-test scheme for multi-channel DRAMs. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings (pp. 245-250). (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2018.8297313

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abstract = "Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.",

keywords = "built-in self-test, channel-based DRAM, DRAM, March test, test",

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Wu, KT, Li, JF, Lo, CY, Lai, JS, Kwai, DM & Chou, YF 2018, A channel-sharable built-in self-test scheme for multi-channel DRAMs. in ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 245-250, 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea, Republic of, 22/01/18. https://doi.org/10.1109/ASPDAC.2018.8297313

A channel-sharable built-in self-test scheme for multi-channel DRAMs. / Wu, Kuan Te; Li, Jin Fu; Lo, Chih Yen et al.
ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 245-250 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, Jin Fu

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AU - Kwai, Ding Ming

AU - Chou, Yung Fa

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AB - Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

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Wu KT, Li JF, Lo CY, Lai JS, Kwai DM, Chou YF. A channel-sharable built-in self-test scheme for multi-channel DRAMs. In ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 245-250. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2018.8297313

A channel-sharable built-in self-test scheme for multi-channel DRAMs

Abstract

Publication series

Conference

Keywords

Access to Document

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Projects

Testing of Emerging Nonvolatile-Based Memories for Iot(2/3)

Testing and Reliability-Enhancement Techniques for Stacked Memories(2/3)

Cite this