A channel-sharable built-in self-test scheme for multi-channel DRAMs

Kuan Te Wu, Jin Fu Li, Chih Yen Lo, Jenn Shiang Lai, Ding Ming Kwai, Yung Fa Chou

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Various multi-channel dynamic random access memories (MC-DRAMs) have been proposed for the demand of high bandwidth. In this paper, we propose a channel-sharable built-in self-test (BIST) scheme for MC-DRAMs. The BIST can apply test patterns and evaluate test responses for multiple channels simultaneously regardless of the difference of the read/write latency among the channels. Therefore, the proposed BIST can reduce the test time. In our simulation cases show that the proposed BIST scheme can achieve about 11% test time reduction in comparison with an existing conventional shared BIST scheme for a two-channel 1G-bit DRAM by consuming about 0.003% additional area cost.

Original languageEnglish
Title of host publicationASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages245-250
Number of pages6
ISBN (Electronic)9781509006021
DOIs
StatePublished - 20 Feb 2018
Event23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
Duration: 22 Jan 201825 Jan 2018

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2018-January

Conference

Conference23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Country/TerritoryKorea, Republic of
CityJeju
Period22/01/1825/01/18

Keywords

  • built-in self-test
  • channel-based DRAM
  • DRAM
  • March test
  • test

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