A Built-in Spice Time-domain Variation Model of the BTI-induced Random Trap Fluctuation (RTF) in 14 nm FinFETs

L. C. Lin, Z. Y. Wang, M. Y. Lee, J. K. Chang, E. R. Hsieh, J. C. Guo, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In the advanced FinFET technology, variability has been one of the main scaling concerns. The undesirable variation sources will be finally reflected in real circuit operation. In this paper, a carrier transport mechanism based on Virtual Source Model was first developed. Then, the BTI-induced degradation of device performance after long time operation is discussed. The technique of Random Trap Profiling is used to profile the lateral trap density in the channel from the source to drain. Then, a variation model from the level of device to circuit was built by Virtual Source Model. Finally, the model was implemented in Spice which can simulate the behavior of basic logic gate.

Original languageEnglish
Title of host publication2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665459792
DOIs
StatePublished - 2022
Event2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022 - Honolulu, United States
Duration: 11 Jun 202212 Jun 2022

Publication series

Name2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

Conference

Conference2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
Country/TerritoryUnited States
CityHonolulu
Period11/06/2212/06/22

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