A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Wei Hsuan Yang; Jin Fu Li; Chun Lung Hsu; Chi Tien Sun; Shih Hsu Huang

doi:10.1109/3DIC48104.2019.9058898

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Wei Hsuan Yang, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun, Shih Hsu Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.

Original language	English
Title of host publication	IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728148700
DOIs	https://doi.org/10.1109/3DIC48104.2019.9058898
State	Published - Oct 2019
Event	2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 - Sendai, Japan Duration: 8 Oct 2019 → 10 Oct 2019

Publication series

Name	IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

Conference

Conference	2019 IEEE International 3D Systems Integration Conference, 3DIC 2019
Country/Territory	Japan
City	Sendai
Period	8/10/19 → 10/10/19

Keywords

3D IC
built-in self-Test
DRAM die
TSV

Access to Document

10.1109/3DIC48104.2019.9058898

Robustness and Reliability Enhancement Techniques for Deep Neural Network Systems(1/3)
Li, J.-F. (PI)
1/08/19 → 31/07/20
Project: Research

Cite this

Yang, W. H., Li, J. F., Hsu, C. L., Sun, C. T., & Huang, S. H. (2019). A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. In IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 Article 9058898 (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/3DIC48104.2019.9058898

@inproceedings{8a579058e4a0474bb0cfa32f904db068,

title = "A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs",

abstract = "Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.",

keywords = "3D IC, built-in self-Test, DRAM die, TSV",

author = "Yang, {Wei Hsuan} and Li, {Jin Fu} and Hsu, {Chun Lung} and Sun, {Chi Tien} and Huang, {Shih Hsu}",

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Yang, WH, Li, JF , Hsu, CL, Sun, CT & Huang, SH 2019, A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. in IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019., 9058898, IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019, Institute of Electrical and Electronics Engineers Inc., 2019 IEEE International 3D Systems Integration Conference, 3DIC 2019, Sendai, Japan, 8/10/19. https://doi.org/10.1109/3DIC48104.2019.9058898

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs. / Yang, Wei Hsuan; Li, Jin Fu ; Hsu, Chun Lung et al.
IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 9058898 (IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

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Robustness and Reliability Enhancement Techniques for Deep Neural Network Systems(1/3)

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