A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs

Wei Hsuan Yang, Jin Fu Li, Chun Lung Hsu, Chi Tien Sun, Shih Hsu Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Three-dimensional (3D) dynamic random access memory (DRAM) using through-silicon-via (TSV) has been proposed to overcome the memory wall. WideIO DRAM is one type of 3D DRAMs. IOs of a WideIO DRAM die are wrapped by a 1149. 1-like boundary scan controlled by a scan controller. In this paper, we propose a built-in-self-Test (BIST) scheme for the post-bond testing of TSVs of a logic-DRAM stack. The BIST circuit implemented in the logic die can generate control signals for the scan controller and test patterns for the testing of TSVs.

Original languageEnglish
Title of host publicationIEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728148700
DOIs
StatePublished - Oct 2019
Event2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 - Sendai, Japan
Duration: 8 Oct 201910 Oct 2019

Publication series

NameIEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

Conference

Conference2019 IEEE International 3D Systems Integration Conference, 3DIC 2019
Country/TerritoryJapan
CitySendai
Period8/10/1910/10/19

Keywords

  • 3D IC
  • built-in self-Test
  • DRAM die
  • TSV

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