A Built-in Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy

Keyphrases

• Built-in Self-repair 100%
• Repair Scheme 100%
• Redundancy 100%
• Semiconductor Memory 100%
• Analysis Module 60%
• Built-in Redundancy Analysis 60%
• Built-in-self-test (BiST) 40%
• Embedded Memory 40%
• Redundancy Analysis Algorithm 40%
• Memory Test 40%
• Redundant Structure 40%
• Test Circuit 20%
• System-on-chip 20%
• Chip Area 20%
• Area Overhead 20%
• On-chip Implementation 20%
• Low Area 20%
• Reconfiguration 20%
• Repair Method 20%
• Repair Design 20%
• Yield Improvement 20%
• Main Memory 20%
• Repair Rate 20%
• Defective Memory 20%
• Manufacturing Yield 20%
• Enhancement Techniques 20%
• Address Remapping 20%

Engineering

• Built-in Self Test 100%
• System-on-Chip 100%
• Experimental Result 50%
• Reliability Availability and Maintainability (Reliability Engineering) 50%
• Test Circuit 50%
• Chip Area 50%
• Area Overhead 50%
• Repair Design 50%
• Reconfiguration 50%
• Normal Modes 50%

Computer Science

• Redundancy Analysis 100%
• Semiconductor Memory 100%
• build-in self-test 40%
• embedded memory 40%
• System-on-Chip 40%
• Experimental Result 20%
• Yield Enhancement 20%
• Main Memory 20%
• Reconfiguration 20%